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| 101 innovation drive san jose, ca 95134 www.altera.com 8B10B encoder/decoder megacore function user guide megacore version: 7.2 document date: october 2007
copyright ? 2007 altera corporation. all righ ts reserved. altera, the programmable solu tions company, the stylized altera logo, specific device des- ignations, and all other words and logos that are identified as tr ademarks and/or service marks ar e, unless noted otherwise, th e trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of the ir respective holders. al- tera products are protected under numerous u.s. and foreign patents and pending app lications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice . altera assumes no responsibility or liability arising out of t he ap- plication or use of any info rmation, product, or service desc ribed herein except as expressly agreed to in writing by altera corporation. altera customers are advised to obtain the latest ve rsion of device specifications before relying on any published in- formation and before placing orders for products or services . ii megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide ug-iped8B10B-1.10 altera corporation megacore version 7.2 iii contents about this user guide ............................................................................. v revision history ............................................................................................................... ......................... v how to contact altera .......................................................................................................... .................. vi typographic conventions ........................................................................................................ ......... 1?vii chapter 1. about this megacore function release information ............................................................................................................ ................... 1?1 device family support .......................................................................................................... ............... 1?1 features ....................................................................................................................... ............................ 1?2 general description ............................................................................................................ ................... 1?2 opencore plus evaluation ....................................................................................................... ....... 1?2 performance .................................................................................................................... ........................ 1?3 chapter 2. getting started design flow .................................................................................................................... ........................ 2?1 8B10B encoder /decoder walkthrough ............................................................................................ 2 ?2 create a new quartus ii project ................................................................................................. ... 2?2 launch megawizard plug-in manager ......................................................................................... 2?4 parameterize ................................................................................................................... .................. 2?6 set up simulation .............................................................................................................. ............... 2?7 generate files ................................................................................................................. ................... 2?8 set constraints ................................................................................................................ ................ 2?10 simulate the design ............................................................................................................ ........... ...... 2?12 ip functional simulation model ................................................................................................. .2?12 compile the design ............................................................................................................. ................ 2?13 program a device ............................................................................................................... ........... ...... 2?13 set up licensing ............................................................................................................... ........... ........ 2?13 chapter 3. specifications functional description ......................................................................................................... ................. 3?1 disparity ...................................................................................................................... ...................... 3?1 generic framing procedure ...................................................................................................... ...... 3?2 character codes ................................................................................................................ ............... 3?3 encoder ........................................................................................................................ ...................... 3?4 decoder ........................................................................................................................ ...................... 3?8 opencore plus time-out behavior ............................................................................................... 3 ?9 parameters ..................................................................................................................... ............ ........... 3?10 signals ........................................................................................................................ .............. ............. 3?10 iv megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide contents altera corporation megacore version 7.2 v 8B10B encoder/decoder megacore function user guide about this user guide revision history the table below displays the revision hi story for the chapters in this user guide. chapter date version changes made all october 2007 7.2 corrected error in text: the dec oder (not the encoder) asserts kerr upon receiving an invalid code. updated discussion of encoder in the specifications chapter and timing diagrams figure 3?5 and figure 3?6 . all may 2007 7.1 added support for arria? gx device family maintenance release; updated pr oduct release information 1 december 2006 7.0 added support for cyclone iii devices. april 2006 1.6.1 updated release information and device family support tables. october 2005 1.6.0 updated release information and device family support tables. june 2004 1.5.0 updated release information and device family support tables. updated performance information. february 2004 1.4.0 updated release information and device family support tables. added opencore plus description. updated performance information. 2 december 2006 6.1 updated screen shots to match new version. april 2006 1.6.1 updated walkthrough instructions. october 2005 1.6.0 updated system requirements june 2004 1.5.0 update system requirements updated the instructions to obtain the 8B10B encoder/decoder megacore ? function. february 2004 1.4.0 added linux instructions. added ip toolbench instructions. added ip functional simulation models information. vi megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide how to contact altera how to contact altera for the most up-to-date information about altera ? products, go to the altera world-wi de website at www.altera.com . for technical support on this product, go to www.altera.com/mysupport . for additional information about altera products, consult the sources shown below. 3 april 2006 1.6.1 added text to encoded latency description. added ?encoder timing diagram?one cycle latency? on page 3?7 . made corrections to clk signal description. removed device family parameter and added registered inputs/outputs parameter. october 2005 1.6.0 removed mercury ? devices from the device family parameter options, and added the hardcopy ? ii and stratix ? ii gx families. june 2004 1.5.0 no changes. february 2004 1.4.0 added running disparity error output ( rderr ) description. added 10b_err special code description. added opencore plus time- out behavior description. added parameters description (table). updated signals tables. chapter date version changes made information type contact (1) technical support www.altera.com/mysupport/ technical training www.altera.com/training/ technical training services custrain@altera.com product literature www.altera.com/literature product literature services literature@altera.com ftp site ftp.altera.com note: (1) you can also contact your local altera sales office or sales representative. altera corporation megacore version 7.2 vii 8B10B encoder/decoder megacore function user guide about this user guide typographic conventions this document uses the typogr aphic conventions shown below. visual cue meaning bold type with initial capital letters command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. example: save as dialog box. bold type external timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and softw are utility names are shown in bold type. examples: f max , \qdesigns directory, d: drive, chiptrip.gdf file. italic type with initial capital letters document titles are shown in italic ty pe with initial capital letters. example: an 75: high-speed board design. italic type internal timing parameters and variables are shown in italic type. examples: t pia , n + 1. variable names are enclosed in angle br ackets (< >) and shown in italic type. example: viii megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide typographic conventions altera corporation megacore version 7.2 1?1 october 2007 8B10B encoder/decoder megacore function user guide 1. about this megacore function release information table 1?1 provides information about this release of the altera ? 8B10B encoder/decoder megacore ? function. device family support megacore functions provide either full or preliminary support for target altera device families: full support means the megacore function meets all functional and timing requirements for the device family and may be used in production designs. preliminary support means the megacore function meets all functional requirem ents, but may still be unde rgoing timing analysis for the device family; it may be used in production designs with caution. table 1?2 shows the level of support offered by the 8B10B encoder/decoder megacore function to each altera device family. table 1?1. 8B10B encoder/decod er megacore function release information item description version 7.2 release date october 2007 ordering code ip-ed8B10B product id 0079 vendor id 6af7 table 1?2. device family support (part 1 of 2) device family support arria ? gx preliminary cyclone ? full cyclone ii full cyclone iii preliminary hardcopy ? ii full 1?2 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 features features support for arria ? gx device family 8b/10b encoding and decoding cascaded encoding and decoding industry compatible special character coding easy-to-use ip megawizard ? interface support for opencore plus evaluation ip functional simulation models for use in altera-supported vhdl and verilog hdl simulators general description encoders and decoders are used for physical layer coding for gigabit ethernet, fibre channel, and other applications. the 8b/10b encoder takes byte inputs, and generates a direct current (dc) balanced stream (equal number of 1s and 0s) with a maximum run length of 5. some of the individual 10-bit codes will have an equal number of 1s and 0s, while others will have either four 1s and six 0s, or, six 1s and four 0s. in the latter case, the disparity between 1s and 0s is used as an input to the next 10-bit code generation, so that the disparity can be reversed, and maintain an overall balanced stream. for this reas on, some 8-bit inputs have two valid 10-bit codes, depending on the input disparity. the altera 8B10B encoder/decoder is a compact, high performance megacore function capable of encoding and decoding in multi-gigabit applications. opencore plus evaluation with altera?s free opencore plus ev aluation feature, you can perform the following actions: simulate the behavior of a me gafunction within your system hardcopy stratix ? full stratix full stratix ii full stratix ii gx full stratix iii preliminary stratix gx full other device families no support table 1?2. device family support (part 2 of 2) device family support altera corporation megacore version 7.2 1?3 october 2007 8B10B encoder/decoder megacore function user guide about this megacore function verify the functionality of your desi gn, as well as evaluate its size and speed quickly and easily generate time-limited device programming files for designs that include megafunctions program a device and verify your design in hardware you only need to purchase a licens e for the megafunction when you are completely satisfied with its functi onality and performance, and want to take your design to production. f for more information on opencore pl us hardware evaluation using the 8B10B encoder/decoder see ?opencore plus time-out behavior? on page 3?9 and an 320: opencore plus ev aluation of megafunctions . performance table 1?3 , table 1?4 , and table 1?5 show the resource utilization and performance of some 8B10B enco der/decoder megacore functions. these results were obtained using the quartus ? ii software version7.1 for the following devices: cyclone ii (ep2c35f484c6) cyclone iii (ep3c80f780c6) stratix ii (ep2s30f484c3) stratix iii (ep3se110f780c2) 1?4 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 performance table 1?3. resource utilization and performance (cyclone ii, cyclone iii) device parameters les f max (mhz) (1) (2) mode of operation register inputs/outputs cyclone ii encoder on 100 250 encoder off 107 454 decoder ? 131 403 cyclone iii encoder on 100 250 encoder off 107 454 decoder ? 131 403 notes to ta b l e 1 ? 3 : (1) f max is for non-cascaded encoders/decoders. (2) these results were obtained with the au to-rom replacement feat ure disabled in the quartus ii software. enabling this feature produces a smaller but slower megacore function. table 1?4. resource utilization and performance (stratix ii) device parameters combinational aluts logic registers f max (mhz) (1) (2) mode of operation register inputs/outputs stratix ii encoder on 61 51 444 encoder off 68 13 585 decoder ? 55 33 447 notes to table 1?4 : (1) f max is for non-cascaded encoders/decoders. (2) these results were obtained with the auto-rom replacement feature disabled in the quartus ii software. enabling this feature produces a smaller but slower megacore function. altera corporation megacore version 7.2 1?5 october 2007 8B10B encoder/decoder megacore function user guide about this megacore function table 1?5. resource utilization and performance (stratix iii) device parameters combinational aluts logic registers f max (mhz) (1) (2) mode of operation register inputs/outputs stratix iii encoder on 60 51 510 encoder off 68 13 675 decoder ? 55 33 520 notes to table 1?5 : (1) f max is for non-cascaded encoders/decoders. (2) these results were obtained with the auto-rom replacement feature disabled in the quartus ii software. enabling this feature produces a smaller but slower megacore function. 1?6 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 performance altera corporation megacore version 7.2 2?1 october 2007 8B10B encoder/decoder megacore function user guide 2. getting started design flow to evaluate the 8B10B encoder/decoder megacore ? function using the opencore plus feature include these steps in your design flow: 1. obtain and install the 8B10B encoder/decoder megacore function. the 8B10B encoder/decoder megacore function is part of the megacore ip library, which is distributed with the quartus ? ii software and downloadable from the altera website, www.altera.com . f for system requirements and installation instructions, refer to quartus ii installation & lice nsing for windows or quartus ii installa tion & licensing for unix & linux workstations on the altera website. figure 2?1 shows the directory structure after you install the 8B10B encoder/decoder, where < path > is the installation directory. the default installation directory on windows is c:\altera\71 ; on unix and linux it is /opt/altera/71 . figure 2?1. directory structure 2. create a custom variation of the 8B10B encoder/decoder megacore function. 3. implement the rest of your design using the design entry method of your choice. ed 8 b10b contains the 8B10B encoder/decoder megacore function files and documentation. doc contains the documentation for the megacore function. lib contains encrypted lower-level design files. 2?2 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 8B10B encoder /decoder walkthrough 4. use the ip functional simulation mo del to verify the operation of your design. f for more information on ip function al simulation models, refer to the simulating altera ip in third-party simulation tools chapter in volume 3 of the quartus ii handbook . 5. use the quartus ii software to compile your design. 1 you can also generate an opencore plus time-limited programming file, which yo u can use to verify the operation of your design in hardware. 6. purchase a license for the 8b 10b encoder/decoder megacore function. after you have purchased a license for the 8B10B encoder/decoder megacore function, follow these additional steps: 1. set up licensing. 2. generate a programming file for the altera ? device(s) on your board. 3. program the altera device(s) with the completed design. 8B10B encoder /decoder walkthrough this walkthrough shows you how to create an 8B10B encoder/decoder megacore function using the mega wizard interface and the quartus ii software. after generating a custom variation of the 8B10B encoder/decoder megacore function, you can incorporate it into your overall project. this walkthrough consists of these steps: create a new quartus ii project launch megawizard plug-in manager parameterize set up simulation generate files set constraints create a new quartus ii project you need to create a new quartus ii project with the new project wizard , which specifies the working directory for the project, assigns the project name, and designates the name of the top-level design entity. altera corporation megacore version 7.2 2?3 october 2007 8B10B encoder/decoder megacore function user guide getting started to create a new project follow these steps: 1. choose programs > altera > quartus ii < version > (windows start menu) to run the quartus ii software . alternatively, you can use the quartus ii web edition software. 2. choose new project wizard (file menu). 3. click next in the new project wizard introduction page (the introduction does not display if you turned it off previously). 4. in the new project wizard: directory, name, top-level entity page, enter the following information: a. specify the working directory for your project. for example, this walkthrough uses the directory: c:\altera\projects\ed8B10B_project b. specify the name of the projec t. this walkthrough uses the project name: ed8B10B_example 1 the quartus ii software automat ically specifies a top-level design entity that has the same name as the project. do not change it. 5. click next to close this page and display the new project wizard: add files page. 1 when you specify a directory that does not already exist, a message asks if the specified directory should be created. click yes to create the directory. 6. if you installed the megacore ip library in a different directory from where you installed the quartu s ii software, you must add the user libraries: a. click user libraries . b. type < path > \ip into the library name box, where < path > is the directory in which you installed the 8B10B encoder/decoder megacore function. c. click add to add the path to the quartus ii project. 2?4 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 8B10B encoder /decoder walkthrough d. click ok to save the library path in the project. 7. click next to close this page and display the new project wizard: family & device settings page. 8. on the new project wizard: family & device settings page, choose the target device family in the family list. 9. the remaining pages in the new project wizard are optional. click finish to complete the quartus ii project. you have finished creating your new quartus ii project. launch megawizard plug-in manager to launch the megawizar d plug-in manager in th e quartus ii software, follow these steps: 1. start the megawizard ? plug-in manager by choosing the megawizard plug-in manager command (tools menu). the megawizard plug-in manager dialog box displays (see figure 2?2 ). 1 refer to the quartus ii help for more information on how to use the megawizard plug-in manager. figure 2?2. megawizard plug-in manager 2. specify that you want to create a new custom megafunction variation and click next . 3. expand the communications > encoding/decoding directory, then click 8B10B encoder-decoder v7.1 . altera corporation megacore version 7.2 2?5 october 2007 8B10B encoder/decoder megacore function user guide getting started 4. choose the device family you want to use for this megacore function, for example stratix ii gx . 5. select the output file type for your design; the megawizard interface supports vhdl and verilog hdl. 6. the megawizard plug-in manager sh ows the project path that you specified in the new project wizard . append a variation name for the megacore function output files < project path >\< variation name >. figure 2?3 shows the megawizard plug-in manager after you have made these settings. figure 2?3. select t he megacore function 7. click next to display the parameter settings page for the 8B10B encoder/decoder megacore function (see figure 2?4 ). 2?6 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 8B10B encoder /decoder walkthrough 1 you can change the page that the megawizard plug-in manager displays by clicking next or back at the bottom of the dialog box. you can move directly to a named page by clicking the parameter settings , simulation model , or summary tab. figure 2?4. parameters parameterize to parameterize your megacore function, follow these steps: 1. select the mode of operation, either encoder or decoder 2. if you selected encoder , turn on the register inputs/outputs check box for a three-cycle latency, or turn off the register inputs/outputs check box for a single-cycle latency. 1 the decoder always has registered inputs and outputs. altera corporation megacore version 7.2 2?7 october 2007 8B10B encoder/decoder megacore function user guide getting started 3. select the mode of operation, either encoder or decoder . 4. if you selected encoder , turn on the register inputs/outputs check box for a three cycle latency, or turn off the register inputs/outputs check box for a single cycle latency. 1 the decoder always has registered inputs and outputs. 5. click next (or the simulation model tab) to display the simulation setup page (see figure 2?5 ). figure 2?5. simulation model set up simulation an ip functional simulation model is a cycle-accurate vhdl or verilog hdl model file produced by the quartus ii software. the model allows for fast function al simulation of ip usin g industry-standard vhdl and verilog hdl simulators. 2?8 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 8B10B encoder /decoder walkthrough c you may only use these models for simulation purposes and expressly not for synthesis or any other purposes. using these models for synthesis create s a nonfunctional design. to generate an ip functional si mulation model for your megacore function, follow these steps: 1. turn on generate simulation model . 2. choose the language you want from the language list. 3. click next (or the summary page) to display the summary page (see figure 2?6 ). figure 2?6. summary page generate files you can use the check boxes in the s ummary page to enable or disable the generation of specified files. a gray checkmark indicates a file that is automatically generated; a red chec kmark indicates an optional file. altera corporation megacore version 7.2 2?9 october 2007 8B10B encoder/decoder megacore function user guide getting started you can click back to display the previous page or click parameters setting , simulation library , or summary page , if you want to change any of the megawizard options. to generate the files, follow these steps: 1. turn on the files you want to generate (see figure 2?6 ). 2. to generate the specified file s and close the megawizard plug-in manager, click finish . 1 the generation phase may take several minutes to complete. when the file generation is complete, you can go to the project directory and view a list of generated files in the file 2?10 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 8B10B encoder /decoder walkthrough set constraints the 8B10B encoder/decoder megacore function variations include a tool command language (tcl) script. us e this tcl script to constrain your design. to run the tcl script in the quartu s ii software, in a win32 operating system, follow either of these sets of steps: 1. select tcl scripts (tools menu) 2. select the applicable tcl file for your variation: < variation name >_ constraints. tcl 3. click run . or 1. click on tc l c o n s o l e under utility_windows (view menu) 2. in the tcl console window, type: source altera corporation megacore version 7.2 2?11 october 2007 8B10B encoder/decoder megacore function user guide getting started 1 depending on the type of constr aints applied by the tcl script, analysis and synthesis may be run twice. for example, if hierarchy independent constraints are needed, the tcl script runs analysis and synthesis befo re applying the constraints. therefore, when you run a full compilation, after running the tcl script, the analysis and synt hesis are run a second time. you can now integrate your custom megacore function variation into your design, simulate, and compile. 2?12 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 simulate the design simulate the design you can simulate your design usin g the generated vhdl and verilog hdl ip functional simulation models. f for more information on ip function al simulation models, refer to the simulating altera ip in third-party simulation tools chapter in volume 3 of the quartus ii handbook . altera also provides a verilog hdl demonstration testbench, including scripts to compile and run the demonstration testbench using a variety of simulators and models. this testbench demonstrates the typical behavior of an 8B10B megacore function, an d how to instantiate a model in a design. the demonstration testbe nch does not perform any error checking. f for a complete list of models or li braries required to simulate the 8B10B encoder/decoder megacore function, refer to the _ run_modelsim.tcl scripts provided with the demonstration testbench. ip functional simulation model to use the demonstration testbench wi th ip functional simulation models in the modelsim ? simulator, follow these steps: 1. start the modelsim simulator. 2. from the modelsim file menu, use change directory to change the working directory to the director y where you created your 8B10B encoder/decoder variation. 3. in the modelsim tr a n s c r i p t window, execute the command do altera corporation megacore version 7.2 2?13 october 2007 8B10B encoder/decoder megacore function user guide getting started compile the design you can use the quartus ii software to compile your design. refer to quartus ii help for instructions on compiling your design. program a device after you have compiled your desi gn, program your targeted altera device, and verify your design in hardware. with altera's free opencore plus eval uation feature, you can evaluate the 8B10B encoder/decoder megacore function before you purchase a license. opencore plus evaluation allows you to generate an ip functional simulation model and pr oduce a time-limited programming file. f for more information on ip function al simulation models, refer to the simulating altera ip in third-party simulation tools chapter in volume 3 of the quartus ii handbo ok version 7.1 . f for more information on opencore pl us hardware evaluation using the 8B10B encoder/decoder, see ?opencore plus time-out behavior? on page 3?9 and an 320: opencore plus ev aluation of megafunctions. set up licensing you need to purchase a license for th e megacore function only when you are completely satisfied with its func tionality and performance, and want to take your design to production. after you purchase a license for 8B10B encoder/decoder, you can request a license file from the altera website at www.altera.com/licensing and install it on your computer. when you request a license fi le, altera emails you a license.dat file. if you do not have in ternet access, contact your local altera representative. 2?14 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 set up licensing altera corporation megacore version 7.2 7.2 3?1 october 2007 3. specifications functional description the megacore ? function consists of an encoder (enc8B10B) and a decoder (dec8B10B). see figure 3?2 on page 3?3 . the encoder encodes one 8-bit byte of data into a 10-bit transmission code, and the decoder decodes a 10-bit code into one 8-bit byte of data. figure 3?1 illustrates the bidirectional conversion process. the eight input bits are named a , b , c , d , e , f , g , h . bit a is the least significant bit (lsb), and bit h is the most significant bit (msb). they are split into two groups: the five-bit group a , b , c , d , e , and the three-bit group f , g , h . the coded bits are named a , b , c , d , e , i , f , g , h , j (the order is not alphabetical). these bits are also sp lit into two groups: the six-bit group a , b , c , d , e , i , and the four-bit group f , g , h , j . figure 3?1. 8B10B conversion in bit serial transmission, the lsb is usually transmitted first, while the msb is usually transmitted last. disparity disparity is the difference between the number of 1s and 0s in the encoded word. 98765432 10 7654321 0 hgfedcba a b c d e i f g h j conversion 8B10B lsb sent first msb sent last 3?2 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 functional description neutral disparity indicates the number of 1s and 0s are equal. positive disparity indicates more 1s than 0s. negative disparity indicates more 0s than 1s. the megacore function is design ed to maintain a neutral average disparity. average disparity determines the direct current (dc) component of a serial line. running disparity is a record of the cumulative disparity of every enco ded word, and is tracked by the encoder. to guarantee neutral aver age disparity, a positive running disparity must be followed by neutral or negative disparity; a negative running disparity must be followed by neutral or positive disparity. the running disparity error output ( rderr ) is asserted when any of the following rules apply: the current running disparity is positive and the 6-bit group has more ones than zeros or is 111000 the current running disparity is negative and the 6-bit group has more zeros than ones or is 000111 the running disparity after 6-bit grou p is positive and the 4-bit group has more ones than zeros or is 1100 the running disparity after 6-bit group is negative and the 4-bit group has more zeros than ones or is 0011 1 rderr is asserted for some invalid 10-bit codes and not for others, strictly based on the rules stated above. the computation of rderr is completely independent of that of the special control character error ( kerr ) signal. 1 a 10-bit code that corresponds to a valid encoding but that has the wrong disparity?though technically an invalid code?does not cause the kerr signal to be asserted. only rderr is asserted. f for details on running disparity rules, refer to the ieee 802.3z specification, pa ragraph 36.2.4.4 . generic framing procedure the 8B10B encoder/decoder megacore function can be used within generic framing procedure (gfp) applications. see figure 3?2 on page 3?3 for an example. altera corporation megacore version 7.2 3?3 october 2007 8B10B encoder/decoder megacore function user guide specifications figure 3?2. 8B10B encoder/decoder gfp typical application on ingress to the transport networ k, if the decoder receives an unrecognized codeword, such as an i llegal codeword or a legal codeword with a running disparity error, it asserts the kerr or rderr signals respectively. by asserting these error signals, the decoder indicates to the mapper that an invalid codeword has been received, the mapper then generates a special control character, the 10b_err code. in addition, the mapper remaps the 8b/10b codewords into 64b/65b codewords before sending the data to the transport network. on egress from the transport ne twork, the demapper decodes the 64b/65b codewords and sends them to the 8b/10b encoder. when the encoder receives the 10b_err code, it sends out one of the two 10-bit illegal codewords with neutral disparity: 001111 0001(rd-) or 110000 1110(rd+), depending on the running disparity. character codes in addition to 256 data characters, the 8b/10b code defines thirteen out- of-band indicators, also called spec ial control characters. the 256 data characters are named d x.y , and the special control characters are named k x.y ?except for the special code 10b_err (see table 3?1 on page 3?4 ). the x value corresponds to the five-bit group, and the y value to the three- bit group. the special control characters indicate, for example, whether the data is idle, test data, or data delimite rs. in applications where encoded characters are transmitted bit-serial ly, the comma character (k28.5) is usually used for alignment purposes as its 10-bit code is guaranteed not to occur elsewhere in the encoded bit stream, except after k28.7 which is normally only sent during diagnostic. (64b/65b encoded) transport network gfp data stream demapper gfp encoder 8b/10b decoder 8b/10b mapper gfp gi g abit ethernet stream (8b/10b encoded) gi g abit ethernet stream (8b/10b encoded) in g ress e g ress 3?4 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 functional description table 3?1 lists the special k codes used by the megacore function. encoder to encode an 8-bit word, the 8-bit value must be applied to the datain inputs and the ena input must be asserted (active high). when one of the thirteen special 10-bit codes is to be inserted, the equivalent 8-bit code is placed on the datain lines and the kin input is asserted. the megacore function performs error checking to ensure the out-of-band 8-bit code is valid. if not, the kerr output is asserted. see table 3?1 for a list of the valid k codes. 1 although the 10b_err code is considered to be an invalid special character, it does not cause the kerr signal to be asserted. idle (k28.5) characters can be automatically inserted when ena is not asserted by asserting the idle_ins input. the encoder encodes invalid characters in the same way it encodes idle (k28.5) codes. the decoder treats invalid characters as idle codes. table 3?1. character codes 10-bit special k codes equivalent 8-bit codes k28.0 8'b000_11100 k28.1 8'b001_11100 k28.2 8'b010_11100 k28.3 8'b011_11100 k28.4 8'b100_11100 k28.5 (1) 8'b101_11100 k28.6 8'b110_11100 k28.7 8'b111_11100 k23.7 8'b111_10111 k27.7 8'b111_11011 k29.7 8'b111_11101 k30.7 8'b111_11110 10b_err 8'b111_11111 note to ta b l e 3 ? 1 : (1) k28.5 is a comma character used for alignment purposes, and to represent the idle code. altera corporation megacore version 7.2 3?5 october 2007 8B10B encoder/decoder megacore function user guide specifications figure 3?3 shows a block diagram of the encoder. figure 3?3. encoder disparity the running disparity can be forced to positive or negative, allowing the user to insert a special resynchronization pattern, or disparity errors. when the rdforce input is asserted, the value on the rdin port is assumed to be the current running disparity. setting rdin to 0 forces the encoder to produce an encoded word wi th positive or neutral disparity. setting rdin to 1 forces the encoder to produce an encoded word with negative or neutral disparity. cascaded encoding two encoders can be cascaded to allow for 16-bit word encoding. the encoders are cascaded by connecting the rdcascade output of the most significant byte (msbyte) encoder to the rdin input of the least significant byte (lsbyte) encoder, and by connecting the rdout output of the lsbyte encoder to the rdin input of the msbyte encoder. these connections ensure proper running disparity computation. the rdforce inputs must be asserted (active high) for the encoders to take into account the value on the rdin inputs, rather than use their internally generated running disparity. both ena inputs must be high or low at the same time. the kin [1] signal relates to datain[15:8] , and kin[0] relates to datain[7:0] . figure 3?4 on page 3?6 shows two encoders connected together to perform cascaded encoding. if the encoded words are to be transmi tted serially, the result of encoding datain[15:8] should be transmitted first. clk reset_n kin ena rdin rdcascade rdout valid kerr datain [7:0] dataout [9:0] rdforce idle_ins 3?6 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 functional description figure 3?4. cascaded encoding note (1) note to figure 3?4 : (1) the ena , idle_ins , and rdforce signals are set high (logic 1). encoding latency when the register inputs/outputs parameter is turned on, the encoder is pipelined, thus it takes three clock cycles for a character to be encoded. the encoded value?corresponding to the values of datain and kin sampled by the encoder on rising edge n ?is output shortly after rising edge n+2 , and is available to be sampled on the rising edge of clock cycle n+3 . (see figure 3?5 on page 3?7 ). to enable cascaded encoding, the data paths fed by the rdforce and rdin inputs are n ot pipelined. because rdforce and rdin are normally only used in cascaded configurations, this should not be a problem. in cases where the rdforce and rdin inputs are to be used in noncascaded configurations, they should be delayed two clock cycles with respect to their corresponding datain and kin values. clk reset_n rdout valid kerr clk reset_n rdcascade valid kerr rdout rdin dataout [9:0] rdcascade rdin [1:0] kin [15:0] datain ena rdforce ena rdforce datain [7:0] datain [15:8] dataout [9:0] kin [0] kin [1] idle_ins idle_ins altera corporation megacore version 7.2 3?7 october 2007 8B10B encoder/decoder megacore function user guide specifications when the register inputs/outputs parameter is turned off, the encoder takes one clock cycle to encode a character. the encoded value? corresponding to the values of datain and kin sampled by the encoder on rising edge n ?is output shortly after rising edge n , and is available to be sampled on the rising edge of clock cycle n+1 . (see figure 3?6 ). figure 3?5. encoder timing diagram?three cycle latency figure 3?6. encoder timing diagram?one cycle latency fibre channel and i eee 802.3z 1000basex in fibre channel and ie ee 802.3z 1000basex applications the encoder does not automatically select the correct 8-bit data for fibre channel eof or 1000basex idle ordered sets. the ru nning disparity based selection of the correct 8-bit data must be made before passing the data to the encoder. clk datain, kin, en, idle_ins dataout, rdout, kerr, valid rdforce, rdin rdcascade a b c d e f g a b c d e a b c d e f ab c def n+1 n+2 n+3 n clk datain, kin, en, idle_ins dataout, rdout, kerr, valid rdforce, rdin rdcascade a b c d e f g a b c d e f a b c d e f g n+1 abcdefg n 3?8 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 functional description decoder data and identified 10-bit special k codes are converted from 10 bits to 8 bits; see table 3?1 on page 3?4 for a list of the valid k codes, and figure 3?1 on page 3?1 for an illustration of the conversion process. when special 10-bit k codes are received, the special k codes are translated to 8-bit values, and the kout signal is asserted. the decoder also checks for invalid 10-bit codes. when the decoder receives an invalid code, it asserts the kerr signal and decodes the value to an arbitrary number. 1 the decoder flags the 10b_err ch aracters as invalid codes and asserts the kerr signal. when the idle_del signal is asserted, it deletes all 10-bit words identified as the special idle character of k28.5. when the receiver detects a disparity error, the rderr signal is asserted. figure 3?7 shows a block diagram of the decoder. figure 3?7. decoder cascaded decoding two decoders can be cascaded to decode two words simultaneously. the decoders are cascaded?in a similar fashion as the encoders?by connecting the rdcascade output of the first decoder to the rdin input of the second decoder, and by connecting the rdout output of the second decoder to the rdin input of the first decoder. the rdforce inputs of both decoders must be tied high. clk reset_n idle_del ena datain [9:0] valid dataout [7:0] kout kerr rderr rdin rdforce rdout rdcascade altera corporation megacore version 7.2 3?9 october 2007 8B10B encoder/decoder megacore function user guide specifications to enable cascaded decoding, the data paths fed by the rdin and rdforce inputs are not pipelined. if th ese inputs are to be used in non- cascaded decoders, they should be delayed by one clock cycle with respect to their corresponding datain and kin inputs. decoding latency the decoder is pipelined, thus it takes two clock cycles for a character to be decoded. the decoded value?corresponding to the value of datain sampled by the decoder on rising edge n ?is output shortly after rising edge n+1 , and is available to be sampled on the rising edge of clock cycle n+2 . (see figure 3?6 on page 3?7 ). figure 3?8. decoder timing diagram opencore plus time-out behavior opencore ? plus hardware evaluation can support the following two modes of operation: untethered ?the design runs for a limited time tethered ?requires a connection between your board and the host computer. if tethered mode is su pported by all megafunctions in a design, the device can operate for a longer time or indefinitely all megafunctions in a device time out simultaneously when the most restrictive evaluation time is reac hed. if there is more than one megafunction in a design, a specific megafunction?s time-out behavior may be masked by the time-out behavior of the other megafunctions. 1 for megacore functions, the unte thered timeout is 1 hour; the tethered timeout value is indefinite. clk datain, ena rdforce, rdin a b c d e f g a b c d e a b c d e f n+1 n n+2 n+3 dataout, kout kerr, rdout, rderr 3?10 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 parameters your design stops working after the hardware evaluation time expires, and the following events occur: for the encoder: the ena input signal is forced low (deasserted) the dataout output is forced to the k28.5 pattern the valid output is forced low (deasserted) for the decoder: the ena input signal is forced low (deasserted) the dataout output is forced to all zeros the valid output is forced low (deasserted) f for more information on opencore plus hardware evaluation, see ?opencore plus evaluation? on page 1?2 and an 320: opencore plus evaluation of megafunctions . parameters table 3?2 shows the 8B10B encoder/decoder function parameters, which can only be set in the megawizard interface (see ?parameterize? on page 2?6 ). signals tables 3?3 and 3?4 show the encoder and decoder signals. table 3?2. 8B10B encoder/decoder parameters parameter value mode of operation encoder or decoder register inputs/outputs on for a three cycle latency. off for a one-cycle latency. table 3?3. encoder signals (part 1 of 2) signal name direction description clk input clock. the input is latched, and the result is output on this clock. there is a one clock cycl e latency between the input and output. reset_n input active low, reset. asynchronously resets all registers in the megacore function. this signal should be deas serted synchronously to the rising edge of clk . kin input command byte indicator. when high, indicates that the input is a command byte, not a data byte. ena input enable encoder signal. when high, indicates that the data currently present on the datain input is to be encoded. altera corporation megacore version 7.2 3?11 october 2007 8B10B encoder/decoder megacore function user guide specifications idle_ins input idle character insert. when high, idle (k28.5) characters are inserted when ena is not asserted. datain[7:0] input data input. this is the 8-bit input word, data or command. rdin input running disparity input. when rdforce is high, the value on this pin is used as the current running disparity instead of the internally generated one. rdforce input force running disparity. when high, the rdin value overrides the internally generated running disparity. kerr output special k character error. this signal is set high when ena and kin are high and the value on datain is not a valid special k character. dataout[9:0] output data output. this is the 10-bit encoded output. valid output valid signal. when high, indicates that a valid encoded word is present on the dataout output. rdout output running disparity output. the current running disparity (after encoding the word present on the dataout output). rdcascade output cascaded running disparity. used when encoders are cascaded. table 3?4. decoder signals (part 1 of 2) signal name direction description clk input clock. the input is latched, and the result output on this clock. there is a three clock cycle latency between the input and output. reset_n input active low, reset. asynchronously resets all registers in the megacore function. this signal must be deas serted synchronously to the rising edge of clk . idle_del input idle delete signal. when high, idle words (k28.5) are removed from the stream (i.e. valid is set low when idle words are received). ena input enable decoder signal. when high, indicates that the data currently present on the datain input is to be decoded. datain[9:0] input data input. this is t he 10-bit encoded input word. rdin input running disparity input. when rdforce is high, the value on this pin is used as the current running disparity instead of the internally generated one. rdforce input force running disparity. when high, the rdin value overrides the internally generated running disparity. table 3?3. encoder signals (part 2 of 2) signal name direction description 3?12 megacore version 7.2 altera corporation 8B10B encoder/decoder megacore function user guide october 2007 signals valid output valid signal. this signal is asserted when ena is asserted and new, non- idle data is present on dataout , even if it is the result of an illegal codeword. if an illegal codeword is received, kerr is also asserted. valid is also asserted for idle characters (k28.5) when ena is asserted and idle_del is not asserted. dataout[7:0] output data output. this is the 8-bit decoded data or command. kout output command output. when high, indicates that the output is a command byte, not a data byte. kerr output special k error. asserted high when an invalid 10-bit word is received, or when a 10b_err character is received. rderr output running disparity error. when high indicates the running disparity rules have been violated. rdout output running disparity output. the current running disparity (after decoding the word present on the dataout output). rdcascade output cascaded running disparity. used when decoders are cascaded. table 3?4. decoder signals (part 2 of 2) signal name direction description |
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